Meta's Broadcom-Designed, TSMC-Made AI Chip Reaches Data Centers in Early 2027

Meta Platforms plans to begin installing a new generation of in-house AI accelerators in its data centers in the first half of 2027, a move the company says will lower the cost and the energy it spends running models across Facebook, Instagram and WhatsApp.

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The chip is the MTIA 450, code-named Arke, and it is the third generation of Meta's Meta Training and Inference Accelerator line. Meta designs it with Broadcom and has TSMC manufacture it, according to a Bloomberg report published on September 15, 2026. The first twelve units arrived from TSMC on September 1, and early results landed within 2 to 3 percent of the performance Meta's own simulations had predicted. On the first day of testing, the team ran models from Meta, DeepSeek and Alibaba on the silicon.

That detail matters more than it first appears. Running three different model families on day one, including two built outside Meta, is an early signal that the chip is being evaluated across a range of architectures rather than tuned to a single internal workload. The first-batch accuracy against simulation is the metric chip teams watch most closely, because a design that misses badly rarely recovers on schedule. Bloomberg reported that the early samples showed no design flaws, while noting that several months of debugging and optimization remain and that TSMC's manufacturing yields are still ramping up.

Twelve chips, one gigawatt

The headline number in Meta's plan is not the size of the first batch. It is the scale the company has committed to next.

Meta says it has committed to more than 1 gigawatt worth of the chips over a 12-month period, measured by power draw, and it expects the rollout to accelerate after that. Power is the practical unit of account for a data-center operator, because it maps directly to how much floor space, cooling and electrical capacity a deployment consumes. A gigawatt of custom accelerators over a year is a commitment large enough to shape Meta's supply chain, not a pilot.

The figure sits inside a far larger build-out. Reuters reported in July 2026 that Meta intends to roughly double its overall computing capacity to 14 gigawatts by 2027, up from about 7 gigawatts this year. The custom chips are one slice of that expansion, alongside purchased GPUs.

What Arke is built to do, and what it is not

MTIA 450 is designed for general-purpose inference, the work of running a trained model to produce answers, rather than for jobs that demand near-instantaneous response times. Meta's own March 2026 technical post explains the reasoning: memory bandwidth is the single most important factor in generative-AI inference performance, so Meta doubled the high-bandwidth memory bandwidth from the previous MTIA 400 to the 450 and introduced low-precision data types tuned for inference. It described that bandwidth as "much higher than that of existing leading commercial products."

The next chip goes further. Meta says MTIA 500 raises HBM bandwidth by another 50 percent over the 450, increases HBM capacity by up to 80 percent, and lifts MX4 throughput by 43 percent. It uses a 2x2 arrangement of smaller compute chiplets surrounded by several HBM stacks and two networking chiplets. MTIA 450 is scheduled for mass deployment in early 2027; MTIA 500 is scheduled for mass deployment during 2027.

The specifications are a direct expression of the workload. Recommendation and ranking models, which have fed Meta's feeds for years, are memory-bound problems, and generative inference has become one too as models grow. A chip that spends its silicon budget on memory bandwidth and aggressive low-precision math is optimized for serving, not for the compute-heavy work of training new frontier models. Meta has said the MTIA line is not intended for training the largest language models, and independent coverage at Hot Chips in August described the MTIA 400 as aimed primarily at LLM training while noting that Nvidia's and AMD's GPUs remain better suited to that job, as The Register reported.

Why inference, and why Olympus was canceled

Meta's focus on inference is a deliberate narrowing. The company had been working toward a chip code-named Olympus that would have handled both training and inference, and it scrapped that effort to concentrate on inference-only designs. Cost was a major factor.

"When you start to build up gigawatts and gigawatts of capacity, you really care about cost," Yee Jiun Song, Meta's vice president of engineering, told Bloomberg. He said a chip that could do both training and inference might be around 30 percent more expensive, a gap he called "completely unacceptable" at that scale.

The arithmetic behind that comment is straightforward. At gigawatt volumes, a 30 percent premium per chip compounds into an enormous sum, and a part that is merely adequate at two jobs can lose to a part that is excellent at one. Splitting the roadmap lets Meta buy merchant GPUs for training, where the workloads and model architectures move fastest and flexibility matters most, while using custom silicon for the steady, high-volume inference that runs on predictable patterns. That is the same split Amazon, Google and Microsoft have converged on, with different emphasis.

Astrid is a month from finishing design

The chip after Arke is already close on paper. Meta expects MTIA 500, code-named Astrid, to complete its design work in about a month and to enter data centers by the end of 2027, with a broader deployment than Arke. Bloomberg reported that Astrid is meant for wider use, which suggests Meta expects it to clear a higher bar on performance per dollar.

After Astrid, Meta intends to shift attention to speed and throughput, and TrendForce noted that fiber-optic interconnect technology could contribute further performance gains. The cadence itself is a strategy: Meta has been releasing MTIA generations at roughly six-month intervals, faster than the annual or slower rhythm typical of merchant AI chips, so it can fold lessons from one generation into the next quickly. Meta has described this "velocity" approach as a way to keep the silicon aligned with fast-moving model architectures.

The custom-silicon wave Meta is joining

Meta is not building in a vacuum. Every major hyperscaler and several AI labs now design their own accelerators for the workloads that dominate their data centers, a shift that has been building for a decade.

Google's TPU is the oldest and most mature program, now eight generations in. Amazon runs Trainium for training and Inferentia for inference, sold as rentable cloud instances. Microsoft's Maia 200, an inference-focused part on TSMC's 3-nanometer process, runs inside Azure. OpenAI unveiled its first custom chip, code-named Jalapeño, with Broadcom in June 2026, an inference-only design slated to deploy by the end of 2026.

Broadcom sits behind several of these efforts. The company co-designs chips for Google, Meta and OpenAI, and industry analysts put its share of the custom accelerator design market near 70 percent. In practice, that means the custom-silicon wave is less a story of companies going it alone than of a small number of design partners, one dominant foundry and a handful of memory suppliers tightening into a new kind of supply chain. All of the major programs, including Meta's, manufacture at TSMC, as Tom's Hardware's survey of the landscape notes.

The memory wall

That shared dependence points to the constraint that may matter most. Every MTIA generation leans heavily on high-bandwidth memory, and HBM is the scarcest input in the AI supply chain right now.

The shortage is not a temporary spike. Research from CSIS described in September 2026 a global memory shortage expected to persist through 2027 and possibly into 2028, driven by the concentration of HBM production among three suppliers and the long lead times required to build new fabs. J.P. Morgan Global Research estimated that DRAM prices would rise more than 400 percent from the start of 2024 to the end of 2026, and Meta itself raised its capital-spending guidance by $10 billion, citing higher AI hardware and memory costs.

Meta's engineers have been candid about the exposure. Song told CNBC earlier this year that the company was "absolutely worried about HBM supply," though he said enough had been secured to support the planned deployments, as TrendForce reported in March. Meta has signed long-term agreements with Samsung Electronics for memory, Sandisk for flash storage and Sumitomo Electric for fiber-optic equipment, according to the Reuters review of an internal memo. Designing a chip around HBM is one bet; getting enough of it, at a tolerable price, is a separate one.

The Nvidia comparison, and why it is unproven

Meta is making a large claim about where its silicon stands. The company says the chips can run AI models more efficiently than "whatever Nvidia is currently shipping," a framing Bloomberg and TrendForce both attributed to Meta.

That claim is unverified. Meta has not published head-to-head benchmarks against Nvidia's current shipping parts, and "more efficient" is not a standardized metric. It could refer to performance per watt, cost per token, throughput per rack or some combination, and the answer may differ by workload. Custom silicon has a long history of beating the previous generation of Nvidia hardware while trailing the current one on raw capability, and the fair comparison depends on which models, batch sizes and precision formats are used. Until independent testing exists, the claim should be treated as a vendor's positioning rather than a measured result.

There is a structural reason to expect real gains in specific cases, though. A chip built only for inference can strip out generality that a merchant GPU must carry, and Meta controls its own serving stack, compilers and workload mix. Companies that know their traffic precisely can capture savings a general-purpose part cannot match. The open question is how much of the claim survives contact with Meta's full production workload.

What to watch

Three things will show whether Meta's chip program delivers on the promise it is making.

The first is whether the 2-to-3-percent simulation gap holds as Meta moves from a dozen engineering samples to volume. Engineering samples flatter a design; production yields, thermal behavior at rack scale and software maturity tend to narrow the gap or widen it, and Meta has said several months of debugging and optimization remain.

The second is HBM supply. Meta's deployment target is denominated in gigawatts, but its chips are denominated in memory bandwidth, and the two are linked. If qualified HBM stays scarce through 2027, even a strong chip can be constrained by what surrounds it.

The third is whether Astrid lands on schedule. A design completion in about a month and deployment by the end of 2027 is an aggressive sequence, and the slip of a single generation is enough to reset the cadence that gives Meta's approach its edge. Nvidia, meanwhile, continues to ship its own next-generation platforms, so the comparison Meta is inviting will keep being tested in public.

For now, the verified facts are narrower than the ambition. Meta has a third-generation inference chip in testing, twelve units in hand, a 1-gigawatt commitment and a successor in design. Whether the economics follow is the part that will be settled in 2027.

Cover: an aerial view of Meta's headquarters in Menlo Park, California, by InvadingInvader (CC BY-SA 4.0) via Wikimedia Commons, cropped to 16:9.